The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a gate line of a fine line width.
As semiconductor devices are highly integrated, a smaller circuit line width is required. The circuit line width is generally determined by a gate line width. Recently, a fine gate line width has been considered very important. In order for insulation between a gate line and a bit line and/or a storage node, an insulation layer forming process and a self aligned contact (SAC) process are performed after forming the gate line. In semiconductor devices having a memory capacity of more than 1 GB, a gate line width of less than 0.1 μm is required for ensuring a process margin in the insulation layer forming process, the SAC process, and so on. On the other hand, the height of the gate line is gradually increased in order to prevent the increase of a gate resistance, which is caused by the reduction of the gate line width.
FIGS. 1A and 1B illustrate a typical method for forming a gate line. Specifically, FIG. 1A is a plan view of a semiconductor device having a gate line, and FIG. 1B is a cross-sectional view taken along a line A-A′ of FIG. 1A. Referring to FIGS. 1A and 1B, an isolation layer 12 is formed over a substrate 11 to define an active region 11A. A gate insulation layer 13 is formed over the substrate 11.
A polysilicon layer 14 and a tungsten (W) layer 15 for a gate electrode and a nitride layer 16 for a gate hard mask are sequentially formed over the gate insulation layer 13 and patterned using a mask and an etch processes, thereby forming a gate line 100. Although not shown in FIGS. 1A and 1B, a contact region is formed within the active region 11A on both sides of the gate line 100. The contact region contacts a bit line or a storage node, which will be formed later.
In the process of forming the gate line, the line width of the gate line is being decreased but its height is being increased. Therefore, the gate line may tilt against an adjacent gate line, so that they come in contact with each other, as indicated by dotted lines in FIGS. 1A and 1B. This will cause defects in semiconductor devices.